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Philips Semiconductors
256 × 8-bit static low-voltage RAM with
I 2 C-bus interface
Product speci?cation
PCF8570
8.3
System con?guration
A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls
the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.
SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER /
RECEIVER
MBA605
Fig.5 System configuration.
8.4
Acknowledge
The device that acknowledges must pull down the SDA
The number of data bytes transferred between the start
and stop conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter.
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal an end of data to the transmitter by not generating
an acknowledge on the last byte that has been clocked out
of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a stop
condition.
handbook, full pagewidth
START
condition
clock pulse for
acknowledgement
SCL FROM
MASTER
1
2
8
9
DATA OUTPUT
BY TRANSMITTER
S
DATA OUTPUT
1999 Jan 06
BY RECEIVER
MBA606 - 1
Fig.6 Acknowledgement on the I 2 C-bus.
6
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